Description

This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flipflop.
Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-vlop to the low level at the next clock pulse. A high level on the input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input

Features

•   High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF)
•   High Output Current: Fanout of 10 LSTTL Loads
•   Wide Operating Voltage: VCC = 2 to 6 V
•   Low Input Current: 1 mA max
•   Low Quiescent Supply Current: ICC (static) = 4 mA max

Ordering Information

Absolute Maximum Ratings