Ultra-low power consumption technology

• V DD = single power supply voltage of 1.6 to 5.5 V

• HALT mode

• STOP mode

High-speed wakeup from the STOP mode is possible.

• SNOOZE mode

RL78 CPU core

• CISC architecture with 3-stage pipeline

• The minimum instruction execution time can be changed from high to ultra-low speed.

- High speed: 0.03125 µs at 32-MHz operation with the high-speed on-chip oscillator clock

- Ultra-low speed: 30.5 µs at 32.768-kHz operation with the subsystem clock

• Multiply/divide/multiply & accumulate instructions are supported.

• Address space: 1 MB

• General-purpose registers: (8-bit register × 8) × 4 banks

• On-chip RAM: 4 KB

Code flash memory

• Code flash memory: 32 or 64 KB

• Block size: 2 KB

• Security function: Prohibition of block erase and rewriting

• On-chip debugging

• Self-programming with boot swapping and flash shield window

Data flash memory

• Data flash memory: 2 KB

• Background operation (BGO): Instructions can be executed from the program memory while rewriting the data

flash memory.

• Number of rewrites: 1,000,000 times (typ.)

High-speed on-chip oscillator

• Selectable from among 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz

• High accuracy: ±1.0% (V DD = 1.8 to 5.5 V, T A = -20 to +85°C)

Middle-speed on-chip oscillator

• Selectable from among 4 MHz, 2 MHz, and 1 MHz with adjustability

Low-speed on-chip oscillator

• 32.768 kHz (typ.) with adjustability

Operating ambient temperature

• T A = -40 to +85°C (2D: Consumer applications)

• T A = -40 to +105°C (3C: Industrial applications)