Ultra-low power consumption technology

• V DD = single power supply voltage of 2.4 to 5.5 V

• HALT mode

• STOP mode

• SNOOZE mode

RL78 CPU core

• CISC architecture with 3-stage pipeline

• Minimum instruction execution time: Can be changed from high speed (0.04167 μs: @ 24 MHz operation with high-

speed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)

• Address space: 1 MB

• General-purpose registers: 8-bit register × 8 × 4 banks

• On-chip RAM: 5.5 KB

Code flash memory

• Code flash memory: 32 KB

• Block size: 1 KB

• Prohibition of block erase and rewriting (security function)

• On-chip debug function

• Self-programming (with boot swap function/flash shield window function)

Data flash memory

• Data flash memory: 2 KB

• Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash

memory.

• Number of rewrites: 1,000,000 times (TYP.)

• Voltage of rewrites: V DD = 2.4 to 5.5 V

High-speed on-chip oscillator

• Select from 48 MHz, 24 MHz, 12 MHz, and 6 MHz

• High accuracy: ±1.0 % (V DD = 2.4 to 5.5 V, T A = -20 to +85°C)

Operating ambient temperature

• T A = -40 to +85°C (A: Consumer applications)

• T A = -40 to +105°C (G: Industrial applications)