Features

■ 32-bit RX CPU core

 Max. operating frequency: 32 MHz

Capable of 50 DMIPS in operation at 32 MHz

 Accumulator handles 64-bit results (for a single

instruction) from 32-bit × 32-bit operations

 Multiplication and division unit handles 32-bit × 32-bit

operations (multiplication instructions take one CPU clock

cycle)

 Built-in FPU: 32-bit single-precision floating point

(compliant to IEEE754)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions, ultra-compact code

 On-chip debugging circuit

■ Low power design and architecture

 Operation from a single 2.7-V to 5.5-V supply

 Three low power consumption modes

■ On-chip code flash memory, no wait states

 128-/64-Kbyte capacities

 On-board or off-board user programming

 For instructions and operands

■ On-chip data flash memory

 4 Kbytes (1,000,000 program/erase cycles (typ.))

 BGO (Background Operation)

■ On-chip SRAM, no wait states

 12 Kbytes of SRAM

■ DMA

 DTC: Five transfer modes

■ Reset and supply management

 Seven types of reset, including the power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 Main clock oscillator frequency: 1 to 20 MHz

 External clock input frequency: Up to 20 MHz

 PLL circuit input: 4 MHz to 8 MHz

 Low-speed on-chip oscillator: 4 MHz

 High-speed on-chip oscillator: 32 MHz ±1%

 IWDT-dedicated on-chip oscillator: 15 kHz

 On-chip clock frequency accuracy measurement circuit

(CAC)